One design, two foundries — only part of it travels.

Architecture & RTL carry over. PDKs, cells, SRAM, hard IP, timing closure & masks get rebuilt per process.

And the weaker variant can set the common performance ceiling.

silicontosoftware.com/tesla-ai5-chip…

#ChipDesign #Semiconductors #TeslaAI5

Tesla is building the same AI5 chip at Samsung AND TSMC.

The physical chips will differ. The goal is for Tesla's software to work identically on both.

That gap is the real engineering story: silicontosoftware.com/tesla-ai5-chip…

#Semiconductors #TeslaAI5 #AIInfrastructure #PCB

A world-class processor can still be crippled by a few inches of material underneath it.

That’s the part of advanced semiconductor scaling that gets considerably less attention.

Everyone watches the transistor.

Meanwhile, the package is becoming brutal.

Take modern heterogeneous integration.

One package may contain:

multiple logic chiplets

12+ HBM stacks

an interposer or RDL structure

microbumps

an organic substrate

high-density microvias

a multilayer system PCB

Now try moving enormous amounts of data through that stack without destroying:

insertion-loss budget

impedance control

timing margin

thermal margin

manufacturing yield

That is not an academic problem.

TSMC is targeting 9.5-reticle-size CoWoS packages capable of integrating 12 or more HBM stacks.

Intel is combining EMIB and Foveros.

UCIe exists specifically because the industry expects more dies to communicate inside the same package.

The dirty secret is that every extra interface creates another place where reality can reject the architecture.

At the substrate and PCB level:

finer line/space hurts manufacturability

stacked microvias increase registration and reliability risk

copper-fill quality matters

fiber weave can create skew

high-loss laminate can consume your SerDes margin

low-loss materials increase cost

additional bonding and assembly steps introduce more yield dependencies

And the tolerances don't magically become easier because the silicon is expensive.

IPC-6012F still matters.

Annular-ring requirements still matter.

Via geometry still matters.

Material selection still matters.

Yield still matters.

This is why I’m skeptical whenever a block diagram makes a multi-chip architecture look effortless.

On PowerPoint, chiplets are boxes with arrows.

On the factory floor, those arrows are real copper, real dielectric, real vias, real registration tolerances, and real scrap risk.

Advanced packaging did not eliminate the scaling problem.

It distributed the problem across more physical layers.

I went deeper into that transition in the full article—from Moore’s Law and A14 through CoWoS, UCIe, microvias, low-loss laminate, KGD testing, and package-level yield.

If you’re evaluating a high-speed design before layout gets locked, the free Advanced Packaging & High-Speed Interconnect Checklist gives you a practical way to review the failure points before they become ECOs, respins, or expensive yield surprises.

Blog: [silicontosoftware.com/moores-law-adv…]

We’re now arguing about transistor dimensions at the scale of a few silicon bonds.

That changes the engineering conversation.

A silicon-silicon bond is roughly 0.22–0.24 nm.

TSMC’s A14 generation is a 1.4-nm-class node targeted for volume production in 2028.

No, that does not mean any transistor feature literally measures 1.4 nm.

That distinction matters.

But the scale tells you what the semiconductor industry is fighting now:

Physics.

As dimensions collapse:

quantum tunneling becomes harder to suppress

electrostatic control becomes harder

leakage becomes harder to manage

power-density tradeoffs get uglier

each incremental shrink costs more engineering effort

The industry has already responded with:

high-k / metal gate

FinFETs

gate-all-around nanosheets

increasingly sophisticated process integration

And transistor scaling is still producing real gains.

TSMC says A14 should deliver more than 20% higher logic density versus N2.

So Moore’s Law is not simply “dead.”

But here’s the part that matters for hardware teams:

The transistor is no longer carrying the entire scaling burden.

Increasingly, system performance has to come from the layers around it:

chiplets

HBM

2.5D / 3D integration

advanced substrates

high-density interconnect

power delivery

thermal management

That means semiconductor scaling is becoming a system integration problem, not just a lithography problem.

And that changes who has leverage.

The packaging engineer matters more.

The substrate supplier matters more.

The PCB stackup matters more.

The interconnect budget matters more.

If you’re designing next-generation hardware, watching node names alone won’t tell you where your next bottleneck is coming from.

I broke down the transistor-to-package shift in the full article, including A14, CoWoS, UCIe, chiplets, HBM, substrate routing, and why advanced packaging comes with its own yield penalties.

For teams working through these constraints, the free Advanced Packaging & High-Speed Interconnect Checklist can be used as a practical review tool before stackup, substrate, and architecture decisions get expensive.

Blog: [silicontosoftware.com/moores-law-adv…]

A 1,500V SiC MOSFET on a datasheet is impressive.

Putting it into an automotive power module that survives for years is the harder problem.

This is where semiconductor discussions often stop too early.

The die might have excellent electrical characteristics.

Then manufacturing gets involved.

Now that device has to be:

attached to a substrate

electrically interconnected

paralleled with other dies

connected through low-inductance busbars

coupled to a cooling system

driven without destructive ringing

repeatedly thermal-cycled for years

And SiC creates some uncomfortable trade-offs.

Fast switching improves efficiency.

Fast switching also makes parasitic inductance much less forgiving.

A poor layout can produce:

voltage overshoot

ringing

EMI

false turn-on

additional device stress

Then there's short-circuit protection.

Typical silicon IGBTs operate with short-circuit withstand times measured in microseconds.

SiC MOSFETs can give the protection circuit an even smaller window.

Peer-reviewed testing on commercial 1.7kV-class SiC devices found short-circuit withstand time falling dramatically as bus voltage increased—from roughly 32 μs at 400V to about 4 μs at 1,100V under the reported test conditions.

Four microseconds.

That's not much time for a protection system to figure out something went wrong.

And qualification doesn't end with the semiconductor.

AEC-Q101 addresses discrete semiconductor qualification.

The complete automotive power module brings another layer of packaging and lifetime validation, with guidelines such as AQG 324 addressing module-level qualification.

This is why I don't look at SiC as simply a “better semiconductor.”

The material solves one set of problems and hands the packaging engineer another set.

That's usually how real engineering works.

Full breakdown of SiC, 1,000V EV architectures and megawatt charging:

[silicontosoftware.com/silicon-carbid…]

Silicon can handle 1,200 volts. That's not why the EV industry is moving to SiC.

This distinction matters.

I've seen semiconductor discussions reduce this to:

“Silicon can't handle the voltage, so manufacturers switched to silicon carbide.”

That's technically wrong.

Silicon IGBTs have been handling high voltage in industrial drives, rail systems and power conversion for decades.

The real question is:

What happens to efficiency, switching loss, thermal load and power density when you try to package that capability inside a vehicle?

That's where SiC becomes interesting.

4H-SiC has a critical electric field roughly an order of magnitude higher than silicon.

That lets semiconductor designers use a much thinner high-voltage drift region.

And that changes the device economics:

lower resistance

lower losses

smaller die

faster switching

higher power density

less cooling burden

That's why 800V architectures increasingly point toward SiC.

And now BYD is pushing the vehicle architecture toward 1,000V with 1,500V-rated SiC devices.

But higher voltage doesn't eliminate the other problems.

At megawatt power levels, engineers still have to deal with:

connector resistance

busbar inductance

insulation coordination

isolation

current sharing

EMI

cooling

This is the part of EV fast charging that rarely makes the marketing deck.

The battery determines how quickly energy can be accepted.

Power electronics determine how efficiently you can get it there.

I broke down the semiconductor physics and system-level trade-offs here:

[silicontosoftware.com/silicon-carbid…]

1,000 amps through an EV charging connector changes the engineering problem completely.

At 1 MW, you aren't designing a bigger phone charger.

You're managing a serious high-power electrical system.

BYD's Super e-Platform is rated around:

1,000 V architecture

1,000 A charging current

Up to 1 MW charging power

10C battery charging

1,500 V-rated SiC power devices

The battery gets most of the headlines.

But there's another problem upstream:

How do you switch and control that much power without turning the power electronics into a thermal liability?

This is where silicon carbide earns its place.

Not because conventional silicon suddenly stops working at high voltage.

It doesn't.

Silicon IGBTs have operated at 1,200V+ for decades.

The problem is what you pay in:

switching losses

conduction losses

cooling

package size

power density

SiC changes that trade-off.

Its much higher critical electric field allows high-voltage devices with thinner drift regions and lower resistance.

That means engineers can build smaller, faster, lower-loss power converters at voltage levels where conventional silicon becomes increasingly difficult to justify.

But don't make the mistake of calling SiC the reason an EV can charge in five minutes.

The battery still has to accept the power.

The connector still has to carry it.

The thermal system still has to remove the heat.

And the grid still has to supply it.

Five-minute charging isn't one breakthrough.

It's several engineering bottlenecks being pushed back at the same time.

Full engineering breakdown:

[silicontosoftware.com/silicon-carbid…]

**AI memory bandwidth keeps climbing.

Unfortunately, heat, current, and PCB real estate don't scale nearly as politely.**

This is the HBM4 problem that gets buried underneath the bandwidth headlines.

HBM4 isn't just stacking DRAM beside a very hot accelerator.

Its base die is becoming a more capable logic layer.

That means more functionality.

And more heat generated underneath multiple layers of DRAM.

At the same time, the compute die beside it is creating a completely different power-delivery problem.

Modern AI accelerator packages can demand more than 1,000 amps on the core compute rail.

To be clear:

That's the compute rail.

Not the HBM4 rail.

But both systems compete for the same brutally limited package and PCB environment.

Now the hardware team has to balance:

PDN impedance

VRM placement

Parasitic inductance

Switching noise

Via current density

Z-axis expansion

Thermal extraction

Interconnect routing

Board and package real estate

Move the regulators closer and the electrical path improves.

But packaging gets harder.

Push power vertically through the PCB and you shorten the current path.

But now the board becomes part of the power-delivery architecture.

Increase package power density and the thermal solution gets more aggressive again.

This is why I don't look at HBM4 as simply a memory upgrade.

It's another example of performance moving faster than the physical infrastructure underneath it.

The memory engineers solved one constraint.

Now packaging, thermal, SI/PI, PCB, and manufacturing engineers inherit the next ones.

That's usually how hardware progress works.

Full engineering breakdown:

[silicontosoftware.com/hbm4-packaging…]

**The most important HBM4 number may not be 2 TB/s.

It may be 2,048.**

That's the width of the data interface.

And unlike a benchmark number, somebody eventually has to manufacture every physical connection behind it.

This is where semiconductor roadmaps run into process engineering.

As interconnect density increases:

Pitch shrinks

Alignment tolerance tightens

Routing gets harder

Yield sensitivity increases

Rework becomes increasingly unrealistic

Thermal paths get more complicated

Hybrid bonding looks like the obvious technical answer.

Remove the microbumps.

Reduce interconnect pitch.

Reduce stack height.

Improve thermal characteristics.

Except manufacturing doesn't select processes because they look better on a PowerPoint slide.

It selects processes based on:

Yield.

Cost.

Qualification.

Throughput.

Repeatability.

Microbumps are already understood.

Hybrid bonding carries a different manufacturing and economic equation.

That's why mass hybrid-bonding adoption is increasingly being pushed toward HBM5 rather than automatically taking over HBM4.

It's the same lesson PCB manufacturers have dealt with for decades:

**The technically superior process doesn't automatically win.

The process you can repeatedly manufacture at acceptable yield usually does.**

HBM4 is simply forcing that trade-off into dimensions measured in microns.

Full engineering breakdown:

[silicontosoftware.com/hbm4-packaging…]

**You can build more HBM.

You can't instantly manufacture more mature advanced-packaging capacity.**

That's a distinction the AI hardware industry is learning the expensive way.

HBM4 is pushing memory bandwidth to extraordinary levels.

But an HBM stack doesn't become an AI accelerator just because the DRAM fab produced it.

It still has to survive:

Die stacking

Base-die integration

Fine-pitch interconnect

Interposer/substrate routing

Package assembly

Thermal qualification

Power integrity

Production yield

And the manufacturing capacity required for that work is heavily concentrated.

Industry estimates put TSMC's share of leading-edge 2.5D advanced packaging somewhere around 90–95%, depending on how the market is defined.

Those are analyst estimates, not audited TSMC numbers.

But the concentration itself is difficult to ignore.

TSMC's own leadership has acknowledged extremely tight CoWoS capacity.

Capacity is expanding aggressively.

Demand is expanding with it.

That's the problem.

A semiconductor fab can produce excellent silicon and still leave customers waiting because another process farther downstream became the constraint.

We've seen this before.

Substrates.

ABF.

MLCCs.

Leadframes.

Now advanced packaging is becoming one of the most strategically important manufacturing layers in AI.

The fastest accelerator you can't package is just expensive inventory.

I broke down where the HBM4 packaging constraint actually sits—and which numbers engineers should watch instead of another bandwidth headline.

[silicontosoftware.com/hbm4-packaging…]

**HBM4 can deliver 2 TB/s per stack.

The harder question is whether we can manufacture enough packages around it.**

HBM4 doubled the memory interface from 1,024 to 2,048 bits.

32 independent channels.

Up to 8 Gb/s.

Up to 2 TB/s per stack.

Impressive numbers.

But every one of those 2,048 data signals eventually becomes a physical interconnect.

And that is where the comfortable spec-sheet discussion ends.

Now you're dealing with:

Finer interconnect pitch

More difficult interposer routing

Stack yield

Package warpage

Thermal resistance

PDN impedance

Advanced-packaging capacity

This is an old manufacturing lesson showing up at a microscopic scale:

Electrical performance is useless if the physical process can't build it economically at volume.

That's why JEDEC's SPHBM4 standard is so interesting.

It reduces the interface from 2,048 data signals to 512 and uses 4:1 serialization to deliver HBM4-class aggregate throughput through an architecture designed for standard organic substrates.

Same basic bandwidth objective.

Very different packaging problem.

HBM4 didn't fail.

Quite the opposite.

The memory technology advanced far enough that the bottleneck is increasingly moving somewhere else.

Into the package.

That's where engineers should be looking next.

I broke down the interconnect, hybrid bonding, SPHBM4, thermal, power-delivery, and manufacturing constraints in the full analysis.

[silicontosoftware.com/hbm4-packaging…]

A 1,000-watt GPU isn't just a thermal problem.

It's an electrical and packaging problem before the coolant ever reaches it.

NVIDIA's DGX B200 documentation allows a maximum GPU power limit of 1,000 W, with a 700 W default configured power limit.

Microsoft's Maia 100 supports 700 W TDP and is provisioned at 500 W.

NVIDIA's full DGX B200 platform is rated for up to 14.3 kW system input across six power supplies in 5+1 redundancy.

Those numbers aren't interchangeable.

A TDP isn't measured workload consumption.

A configured power limit isn't actual instantaneous draw.

And system input power certainly shouldn't be divided by GPU count and called GPU power.

But they illustrate the same engineering problem:

Current has to physically reach the silicon.

As package power rises, the PDN has to carry enormous current through:

package substrates

power planes

vias

interconnect structures

voltage-regulation stages

At the same time, the package has another problem.

HBM wants bandwidth.

Lots of it.

That means dense high-speed routing between compute and memory.

So now two critical systems are drawing from the same finite package design budget:

Power delivery.

Signal connectivity.

They may occupy dedicated structures and layers, but they still compete for:

layer count

via resources

package thickness

routing area

thermal headroom

manufacturing tolerance

This is why simply saying:

“The next AI chip will consume more power”

misses most of the engineering.

The question is:

Can you deliver that power, remove the heat, maintain signal integrity, manufacture the package reliably, and do it thousands of times?

A chip specification tells you what the silicon can theoretically do.

Packaging tells you whether you can deploy it.

Full technical breakdown:

[silicontosoftware.com/ai-chip-packag…]

#PowerElectronics #AIHardware #AdvancedPackaging #DataCenters #Semiconductors

A $12.2 billion semiconductor headline sounds like a finance story.

Look underneath it.

It becomes a manufacturing story.

On August 18, 2026, Marvell issued Google a warrant covering up to 58,970,907 shares at an exercise price of $206.58 per share.

Aggregate exercise value:

About $12.2 billion.

But the interesting part isn't the number.

It's how most of the warrant vests.

The remaining shares vest across 240 tranches tied to Google's purchasing volume.

One tranche for every $500 million in qualifying Custom Products revenue Marvell books from Google.

And Marvell's filing uses a very important word:

Discretionary.

This is NOT a guaranteed Google purchase commitment.

It does NOT publicly guarantee:

CoWoS capacity

packaging allocation

substrate supply

wafer starts

queue priority

Those claims would go beyond the filing.

But the structure still tells engineers something useful.

Google expects custom silicon procurement to matter enough that Marvell's equity upside is being tied directly to the scale of future purchases.

That's a much more interesting signal than another benchmark chart.

Because semiconductor capacity doesn't appear because somebody finished RTL.

Wafer starts take planning.

HBM takes planning.

Substrates take planning.

Advanced packaging takes planning.

And capacity expansion requires visibility into future demand.

The semiconductor companies that understand demand years before everyone else can position manufacturing capacity accordingly.

That's why I think engineers should watch procurement structures and supply-chain commitments alongside architecture announcements.

The chip tells you what a company designed.

The supply chain tells you what it thinks it can actually ship.

Full analysis:

[silicontosoftware.com/ai-chip-packag…]

#SemiconductorIndustry #SupplyChain #Google #CustomSilicon #AdvancedPackaging

A $12.2 billion semiconductor headline sounds like a finance story.

Look underneath it.

It becomes a manufacturing story.

On August 18, 2026, Marvell issued Google a warrant covering up to 58,970,907 shares at an exercise price of $206.58 per share.

Aggregate exercise value:

About $12.2 billion.

But the interesting part isn't the number.

It's how most of the warrant vests.

The remaining shares vest across 240 tranches tied to Google's purchasing volume.

One tranche for every $500 million in qualifying Custom Products revenue Marvell books from Google.

And Marvell's filing uses a very important word:

Discretionary.

This is NOT a guaranteed Google purchase commitment.

It does NOT publicly guarantee:

CoWoS capacity

packaging allocation

substrate supply

wafer starts

queue priority

Those claims would go beyond the filing.

But the structure still tells engineers something useful.

Google expects custom silicon procurement to matter enough that Marvell's equity upside is being tied directly to the scale of future purchases.

That's a much more interesting signal than another benchmark chart.

Because semiconductor capacity doesn't appear because somebody finished RTL.

Wafer starts take planning.

HBM takes planning.

Substrates take planning.

Advanced packaging takes planning.

And capacity expansion requires visibility into future demand.

The semiconductor companies that understand demand years before everyone else can position manufacturing capacity accordingly.

That's why I think engineers should watch procurement structures and supply-chain commitments alongside architecture announcements.

The chip tells you what a company designed.

The supply chain tells you what it thinks it can actually ship.

Full analysis:

[silicontosoftware.com/ai-chip-packag…]

#SemiconductorIndustry #SupplyChain #Google #CustomSilicon #AdvancedPackaging

Google, Amazon, and Microsoft aren't building “fixed-function” AI chips.

That description is technically wrong.

And it hides the real trade-off behind custom silicon.

Google TPU.

Amazon Trainium.

Microsoft Maia.

These are domain-specific accelerators.

But they're still programmable.

Google's TPU includes matrix compute alongside programmable vector and scalar processing.

Trainium exposes tensor, vector, scalar, and general-purpose SIMD engines.

Maia includes programmable vector processing around a custom instruction set.

So the real comparison isn't:

Programmable GPU vs. fixed ASIC.

It's:

Generality vs. specialization.

A GPU spends silicon, power, and engineering resources supporting a very broad range of parallel workloads.

A hyperscaler ASIC can narrow the target.

That can improve efficiency.

But specialization creates another problem.

If the workload changes enough, eventually the architecture may have to change with it.

Google's latest TPU generation makes the point particularly well.

For the first time, Google split its eighth-generation TPU into two designs:

TPU 8t — training

TPU 8i — inference

Not because the previous architecture “failed.”

Google says the requirements of those workloads have diverged enough to justify specialization.

That distinction matters.

Custom silicon doesn't eliminate engineering cost.

It moves the optimization boundary.

You trade some generality for efficiency.

Then you need enough workload volume to justify the silicon program, software stack, validation, packaging, and deployment infrastructure behind it.

That's why custom AI silicon makes enormous sense for hyperscalers.

And considerably less sense for almost everyone else.

Full engineering breakdown:

[silicontosoftware.com/ai-chip-packag…]

#AIChips #Semiconductors #CustomSilicon #GPU #HardwareEngineering

You can finish the AI chip design and still wait months to actually build it.

That's the part of the AI chip race most coverage misses.

Everyone talks about:

NVIDIA GPUs

Google's TPUs

Amazon Trainium

Microsoft Maia

TOPS

FLOPS

performance per watt

But a finished die isn't a finished accelerator.

At the high end, you're dealing with an entire manufacturing system:

Compute silicon.

HBM stacks.

Interposers.

RDL structures.

Organic substrates.

Microbumps.

Power delivery.

Thermal interfaces.

Liquid cooling.

And every additional layer introduces another manufacturing constraint.

This is why advanced packaging capacity matters so much.

TSMC has spent years expanding CoWoS capacity because designing the accelerator isn't enough.

You need the physical capacity to package it at volume.

And here's the uncomfortable part:

A better benchmark doesn't move you forward in the packaging queue.

Manufacturing capacity does.

That's why I think engineers evaluating the AI hardware race should pay less attention to isolated chip specifications and more attention to:

advanced-packaging capacity

HBM availability

substrate capability

package yield

power delivery

cooling

actual shipment volume

The AI chip war isn't happening only at the transistor level.

A significant part of it is happening after wafer fabrication.

I broke down the engineering behind that bottleneck here:

[silicontosoftware.com/ai-chip-packag…]

#Semiconductors #AdvancedPackaging #AIHardware #HBM #Engineering

A photonic link working in the lab is not the same thing as manufacturing thousands of them at acceptable yield.

PCB manufacturing taught me to be suspicious whenever the industry says:

"The technology works."

Fine.

Can you build it repeatedly?

Can you align it?

Can you test it?

Can you thermal-cycle it?

Can you repair it?

And can you do all of that without destroying your yield?

That's where co-packaged optics gets much more interesting.

The photonic engine sits next to the switch ASIC specifically to shorten the high-speed electrical path.

Good idea.

Then manufacturing inherits another problem:

Getting light reliably from silicon into fiber.

Depending on the coupling architecture, alignment requirements can move from low-single-digit microns into much more forgiving ranges when mode expansion, microlenses, SiN/polymer redistribution, or other coupling approaches are used.

That's not a small manufacturing detail.

It's the difference between demonstrating a device and building a production process around it.

And alignment isn't the only issue:

optical coupling loss
package thermal gradients
wavelength stability
assembly throughput
test methodology
optical-engine reliability
laser serviceability
production yield

This is why I don't think the most important CPO number over the next few years will be another bandwidth headline.

I'll be watching production optical-coupling yield.

Because semiconductor history keeps teaching the same lesson:

The device gets the keynote.

Manufacturing decides whether anybody can actually buy it.

I broke down the packaging side of co-packaged optics — including the connection to PCB manufacturing and advanced packaging — here:

[silicontosoftware.com/co-packaged-op…]

For hardware and manufacturing teams preparing for optical I/O, keep the full article as a practical engineering reference for the packaging, alignment, reliability, and yield questions that need to be answered before volume production.

The expensive part of a degraded 224G signal isn't just the lost dB. It's the watts you spend trying to recover it.

That changes how I look at the copper-versus-photonics debate.

Copper channels can absolutely go faster.

Engineers have an impressive toolbox:

FFE
CTLE
DFE
DSP
FEC

But signal recovery isn't free.

As channel loss gets harder to close, the electronics required to compensate generally become more complex — and often consume more power.

Then that power becomes heat.

And here's the uncomfortable part:

That SerDes is sitting beside silicon whose entire reason for existing is computation.

So inside a fixed rack power and cooling envelope, interconnect power competes with compute power.

That's why the transition toward photonics isn't really:

Copper = slow
Light = fast
That's the marketing version.

The engineering version is:

How many watts does it cost to move each bit where it needs to go?

Silicon photonics changes that equation because waveguide propagation loss does not increase with symbol rate in the same way electrical channel attenuation rises with frequency.

It doesn't make optical links lossless.

Lasers consume power.
Modulators have losses.
Couplers have losses.
Receivers consume power.
Thermal tuning can consume power.

But the scaling mechanism is different.
And as AI clusters push toward 224G electrical interfaces and eventually 448G-class links, that difference starts becoming architecturally important.
I went deeper into the physics, SerDes trade-offs, silicon photonics, WDM and co-packaged optics here:
[silicontosoftware.com/co-packaged-op…]
If you're evaluating next-generation AI hardware, use the full breakdown as a practical reference for separating the bandwidth problem from the power problem.

224G doesn't kill copper. It makes every millimeter more expensive.

That's the distinction getting lost in most discussions about AI networking.

At 224G PAM4, OIF framework-era targets span roughly:

15 dB — XSR
32 dB — VSR
35 dB — MR
40 dB — LR

And here's what that can mean on an actual PCB.

In one representative 60 mm channel example:

112G @ 28 GHz: <10 dB insertion loss

224G @ 56 GHz: 18–20 dB

Same length.

Same basic routing problem.

Very different channel margin.

You can fight back.

Better laminate.
Lower-profile copper.
Backdrilled vias.
Cleaner launches.
More aggressive equalization.
Different floorplanning.
We've been doing exactly that for generations.
But none of those tricks repeal skin effect or dielectric loss.
And that's why I think saying "copper is dead" misses the engineering story.
Copper isn't dead.
Its efficient reach is shrinking.

That distinction matters because once your channel budget starts dictating ASIC placement, board architecture, power consumption, and cooling requirements, interconnect stops being a routing problem.

It becomes a system architecture problem.

That's where co-packaged optics enters the conversation.

Not because photons are fashionable.

Because moving the electro-optical conversion closer to the ASIC can eliminate a significant portion of the lossy electrical path.

I broke down the 224G channel problem, CPO architecture, and the manufacturing constraints behind it here:

[silicontosoftware.com/co-packaged-op…]

For engineers working on high-speed hardware, save the article as a practical reference for evaluating where copper still makes sense — and where optical I/O starts becoming part of the architecture.

Moving the Fab Doesn't Move the Supply Chain

A semiconductor fab can move 7,000 miles and still depend on the same concentrated Asian supply chain.

That is the part of semiconductor reshoring that deserves more engineering scrutiny.

TSMC's Arizona commitment has grown from $12 billion in 2020 to $265 billion in 2026.

Ten fabs are planned.

Two advanced-packaging facilities.

An R&D center.

That is serious industrial capacity.

But building fabs is not the same thing as recreating an ecosystem.

A leading AI accelerator depends on far more than wafer fabrication:

Advanced packaging

HBM integration

IC substrates

ABF dielectric film

Specialty chemicals

Packaging equipment

Qualified material stacks

Experienced process engineers

Yield-learning infrastructure

Each layer has its own supplier base.

Its own capacity curve.

Its own qualification clock.

And its own geographic concentration.

TSMC itself has said that U.S. fab-building and facility costs run roughly 4–5× Taiwan levels.

But cost isn't even the hardest problem.

The harder problem is reproducing decades of supplier density and manufacturing knowledge.

Taiwan's semiconductor advantage was never one factory.

It was an ecosystem.

Arizona is building a serious alternative manufacturing base.

But hardware executives should distinguish between:

geographic diversification

and

supply-chain independence.

They are not the same thing.

Moving wafer fabrication reduces one concentration risk.

It does not automatically eliminate the dependencies underneath the package.

For engineering and sourcing teams, that means supply-chain mapping has to extend past Tier 1.

Sometimes the component most likely to stop production is three or four manufacturing layers below the logo on the datasheet.

Free Engineering Resource:

[silicontosoftware.com/the-ai-hardwar…]

Use it to expose second- and third-tier dependencies before they become schedule problems.

Full technical analysis:

[silicontosoftware.com/tsmc-arizona-b…]