Here is our paper titled "PhysioWave-T: Token-Efficient Wavelet Foundation Models for Biosignals" showing that a biosignal foundation model can accommodate heterogeneous acquisition without paying for it in sequence length. See: arxiv.org/pdf/2611.08969
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We are sharing some impressions and our posters from the ETH Launch day. It was a pleasure to meet you, all! You can find PULP posters here: pulp-platform.org/docs/ethlaunch… & pulp-platform.org/docs/ethlaunch… @yichao_zh
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Greetings from Granada, the venue of the Turandot (TUning Risc-V to Automotive Needs & Different Other Themes) kick-off meeting where we are with Frank, Hong and Navaneeth presenting our work on CVA6 & AraXL with focus on automotive applications. Read more chips-ju.europa.eu/Project-detail…
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We are thrilled to let you know that the registration for #EFCL Summer School on Open Source IC and System Design 5 - 9th July 2027, in Bari, Italy is officially open! Four parallel tracks + PULP LX event, read more here efcl.ethz.ch/events/efcl-su…. More info coming soon!
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We have also published Luca's slides " Leveraging an open ISA from Handcrafted to Agentic Design" presented at the 1st Workshop on Virtual ISA for Rapidly Evolving Architectures in Athens. See pulp-platform.org/docs/visa2026/… visaworkshop.github.io/2026/
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Our team is currently at ETH Launch 2026 to showcase our chip design and embedded systems/wearable activities luma.com/4cp2kru3?lm_so…. Come by, the event takes place in the main building of ETH Zurich today until 19:00.
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Our recent paper “Superscalar Loop Processors” exploits loop repetition to run superscalar execution without the overhead of a standard out-of-order processor. Our RISCV Schnizo's area efficiency: +72% vs. Snitch, +85% vs. Spatz on linear algebra workloads arxiv.org/abs/2611.01904
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The slides from Luca's talk "Energy efficiency and Power management for AI accelerators - Tackling the MW rack challenge" presented at the "Sustainable Computing Architecture: From Silicon to Datacenter" workshop in Athens are available online: sustain-microarch.github.io/resources/Beni…
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The live demo video accompanying Giusy's IEEE SMC award winning paper "A Wearable Multimodal Ultrasound+Inertial System for Real-Time Virtual Reality Interaction" is now available on our Youtube channel: youtu.be/lGVLsPpW-V0?si…. You can find the paper here arxiv.org/abs/2606.17741
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#HIPEACInfo79 is out! Apart from quantum computing, you can read about events & projects we are involved in, such as #ACACES, SwissChips & the best paper at EuroMicro DSD: hipeac.net/news/magazine/…. Wishing you a nice weekend!
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We introduce "RTSM: Adapting Recursive Models to Multivariate Time-Series Classification" through a learned temporal tokenizer, single-state weight-tied refinement & a pooled sequence-level readout. See our paper arxiv.org/abs/2610.23353
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PULP Platform retweeted
We need a strong suite of silicon proven open source designs, and here it is!
We are delighted to announce the launch of the PULP benchmark suite. github.com/pulp-platform/…. It is a collection of practical SystemVerilog designs, with a basic synthesis script with Yosys, a file list, Verilator support & SDC files for ASAP7. Prepared partly for ODE4EC project.
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We are delighted to announce the launch of the PULP benchmark suite. github.com/pulp-platform/…. It is a collection of practical SystemVerilog designs, with a basic synthesis script with Yosys, a file list, Verilator support & SDC files for ASAP7. Prepared partly for ODE4EC project.
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We introduce Spatial-TRM, a compact recursive model with frozen vision-language features, a convex region decoder, and just 11.2M trainable parameters. Check out "Look, Reason, Draw a Region: Recursive Refinement for Spatial Context Prediction" arxiv.org/abs/2610.23302
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PULP Platform retweeted
Monte Cimone v3 is a major leap forward in HW and SW maturity and competitiveness for the #RISCV HPC ecosystem! @e4company @Cineca1969
Assessing the competitiveness of #RISCV against established x86 and Arm processors is difficult. We address this problem in "Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads". See arxiv.org/pdf/2610.32632
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Assessing the competitiveness of #RISCV against established x86 and Arm processors is difficult. We address this problem in "Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads". See arxiv.org/pdf/2610.32632
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Check out now Tim's completed doctoral thesis "Scalable Interconnects for Integrated Accelerators" in the ETH Zurich Research Collection. See research-collection.ethz.ch/entities/publi… @fischetim
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You can now find and download Marco's PhD thesis "Many-Core Programmable Clusters for Open, Software-Defined, and AI-Native Radio Access Networks" in the ETH Zurich Research Collection: research-collection.ethz.ch/entities/publi… @MarcoBertuletti
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We are delighted to introduce our new colleague Yuhan! Yuhan will be focusing his research on MAGIA platform integration and deployment for AI models. His research interests include computer architecture and AI accelerator design. Welcome to the team!
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We are excited to present Thomy, the first chip we made with an openPDK ICsprout55. Check out asic.ethz.ch/2026/Thomy.html & github.com/openecos-proje….
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