@tomdabassman Europas Weg zur Chip-Unabhängigkeit: Das #DARE-Projekt designt eigene KI- & Supercomputer-Prozessoren auf Open-Source-Basis (#RISCV). Schutz vor US-Exportkontrollen & Hardware-Spionage. Gefertigt wird das EU-Design aktuell im Tape-Out-Verfahren bei TSMC.

@KrahMax Europas Weg zur Chip-Unabhängigkeit: Das #DARE-Projekt designt eigene KI- & Supercomputer-Prozessoren auf Open-Source-Basis (#RISCV). Schutz vor US-Exportkontrollen & Hardware-Spionage. Gefertigt wird das EU-Design aktuell im Tape-Out-Verfahren bei TSMC.

Todays Tutorial [October 23, 2026]

Lesson 334: Hacking RISC-V Course (Chapter 2: Setup Environment)

#STEM #Embedded #RISCV #ReverseEngineering

github.com/mytechnotalent…

Big shoutout to David Patterson! 🌟 A Google Fellow and UC Berkeley professor emeritus, he helped give us RISC and RAID, co-authored Google's TPU papers and MLPerf Training, and co-wrote seven books.

…dstatesofamericasuperintelligence.com/people/david-p…

#RISCV #AI #Computing

Todays Tutorial [October 22, 2026]

Lesson 333: Hacking RISC-V Course (Chapter 1: Why RISC-V)

#STEM #Embedded #RISCV #ReverseEngineering

github.com/mytechnotalent…

Meet T2M-IP at ICCAD EXPO 2026!
Explore production-proven RISC-V CPU IP cores powering next-gen SoC innovation.
📅 Nov 19–20, 2026
📍 Beijing, China | Booth L074
🤝 Schedule a Meeting: t-2-m.com/event/iccad-20…
#ICCAD2026 #T2MIP #RISCV #SemiconductorIP #SoCDesign

Where does RISC-V stand in high-performance computing?
Monte Cimone v3 puts #RISCV to the test.
The third iteration of this RISC-V-based HPC testbed uses the Sophon SG2044 processor and evaluates its performance, scalability, and energy efficiency against leading @Intel and NVIDIA platforms.
The results show significant gains over earlier versions of Monte Cimone, including 3.08 GFLOPs/W in energy efficiency, around 10× the efficiency of MCv1.
Explore the project and see how RISC-V is performing in the world of #HPC.
👉 Check out this project: hubs.la/Q04yq1C10

6/6 ขีดความสามารถทางวิศวกรรมที่พร้อมรองรับการใช้งานจริงในภาคธุรกิจและสถาบัน 🚀 #RialoTech #RISCV #SVM

Карта производительных риск5-ядер быстро пополняется

Обновления:
— добавлено китайское ядро UltraRISC UR-CP400 (3)
— Qualcomm купила калифорнийскую Akeana со всеми сотрудниками и патентами (30)

Qualcomm теперь владеет двумя риск5 стартапами — Ventana и Akeana

#р5 #riscv

Sharing moments from “Power Electronics Innovation Across Asia” ⚡️

Great to connect face-to-face with industry peers and showcase StarFive’s RISC-V edge gateway, industrial firewall, and JH-B100 BMC solution.

#RISCV #PowerElectronics #pcim

💰 AI芯片公司Tenstorrent融资15亿美元

10月19日宣布完成E轮，投后估值62亿美元。资金用于扩大Galaxy服务器部署及RISC-V芯片业务。

这是融资估值，不是营收。你看好NVIDIA之外的路线吗？
tenstorrent.com/newsroom/tenst…
#Tenstorrent #AI芯片 #RISCV

Where does RISC-V stand in high-performance computing?
Monte Cimone v3 puts #RISCV to the test.
The third iteration of this RISC-V-based HPC testbed uses the Sophon SG2044 processor and evaluates its performance, scalability, and energy efficiency against leading @Intel and NVIDIA platforms.
The results show significant gains over earlier versions of Monte Cimone, including 3.08 GFLOPs/W in energy efficiency, around 10× the efficiency of MCv1.
Explore the project and see how RISC-V is performing in the world of #HPC.
👉 Check out this project: hubs.la/Q04yq1C10

Alibaba’s RISC-V IP powers over 6 billion shipped chips as tech giant targets AI, autos | South China Morning Post

Read the article on the quoted post.

#SCMP #Alibaba #RISCV #AI

Mainline Linux boots to a BusyBox shell on Vreteno, our RISC-V core written in TxHDL: OpenSBI, Sv32 virtual memory and 1 GiB of DDR3, on an Artix-7 board at 100 MHz.

hdlfactory.com/post/2026/10/0…

#RISCV #Linux #FPGA

Alibaba’s RISC-V IP powers over 6 billion shipped chips as tech giant targets AI, autos | South China Morning Post

#SCMP #Alibaba #RISCV #AI
scmp.com/tech/big-tech/…

Tenstorrent raised $1.5B in a Series E at a $6.2B valuation, led by Trace Capital and Innovation X. The money goes to ramping up Galaxy server production, RISC-V research and global hiring.

siliconangle.com/2026/10/19/chi…

#AIChips #Tenstorrent #RISCV #Hardware #TechNews

Where does RISC-V stand in high-performance computing?
Monte Cimone v3 puts #RISCV to the test.
The third iteration of this RISC-V-based HPC testbed uses the Sophon SG2044 processor and evaluates its performance, scalability, and energy efficiency against leading @Intel and NVIDIA platforms.
The results show significant gains over earlier versions of Monte Cimone, including 3.08 GFLOPs/W in energy efficiency, around 10× the efficiency of MCv1.
Explore the project and see how RISC-V is performing in the world of #HPC.
👉 Check out this project: hubs.la/Q04yq1C10

Where does RISC-V stand in high-performance computing?
Monte Cimone v3 puts #RISCV to the test.
The third iteration of this RISC-V-based HPC testbed uses the Sophon SG2044 processor and evaluates its performance, scalability, and energy efficiency against leading @Intel and NVIDIA platforms.
The results show significant gains over earlier versions of Monte Cimone, including 3.08 GFLOPs/W in energy efficiency, around 10× the efficiency of MCv1.
Explore the project and see how RISC-V is performing in the world of #HPC.
👉 Check out this project: hubs.la/Q04yq1C10

Where does RISC-V stand in high-performance computing?
Monte Cimone v3 puts #RISCV to the test.
The third iteration of this RISC-V-based HPC testbed uses the Sophon SG2044 processor and evaluates its performance, scalability, and energy efficiency against leading @Intel and NVIDIA platforms.
The results show significant gains over earlier versions of Monte Cimone, including 3.08 GFLOPs/W in energy efficiency, around 10× the efficiency of MCv1.
Explore the project and see how RISC-V is performing in the world of #HPC.
👉 Check out this project: hubs.la/Q04yq1C10

Where does RISC-V stand in high-performance computing?
Monte Cimone v3 puts #RISCV to the test.
The third iteration of this RISC-V-based HPC testbed uses the Sophon SG2044 processor and evaluates its performance, scalability, and energy efficiency against leading @Intel and NVIDIA platforms.
The results show significant gains over earlier versions of Monte Cimone, including 3.08 GFLOPs/W in energy efficiency, around 10× the efficiency of MCv1.
Explore the project and see how RISC-V is performing in the world of #HPC.
👉 Check out this project: hubs.la/Q04yq1C10